Phase-locked loop circuits are commonly used in applications that rely on stable and programmable output frequencies. A typical PLL may be provided in conjunction with a voltage-controlled oscillator (VCO) to produce a desired output frequency that is phase-locked to a reference frequency from a local oscillator, for example. More specifically, a PLL may include a feedback divider for generating an output frequency as a function of programmable ratios and the VCO output, and a phase detector for monitoring phase differences between the reference frequency and the divided output frequency. In addition, a PLL may include a charge pump for generating a signal that is proportional to the phase difference assessed by the phase detector. In response to the charge pump signal, a loop filter of the PLL can be used to output the appropriate voltage or current to adjust the VCO and the output frequency thereof to match the phase of the reference frequency.
Due to the initially arbitrary phase-offset, there are certain delays inherently associated with the phase-matching processes of conventional PLL circuits. Upon startup, for instance, the PLL can incur at least some delay while assessing the phase offset and reducing the offset over one or more cycles. Such delays can adversely affect not only the overall performance of the PLL, but may also contribute to the collective delays associated with other devices relying on the accuracy of the PLL. These delays may further translate into an increase in overall energy consumption, and in relation to mobile or portable electronic devices, a decrease in battery life. A need therefore exists for more efficient PLLs.